publication order number: mmft3055v/d ? semiconductor components industries, llc, 2006 august, 2006 ? rev. 4 1 mmft3055v power mosfet 1 amp, 60 volts n ? channel sot ? 223 these power mosfets are designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. features ? avalanche energy specified ? i dss and v ds(on) specified at elevated temperature ? pb ? free package is available maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit drain ? to ? source voltage v dss 60 vdc drain ? to ? gate voltage (r gs = 1.0 m ) v dgr 60 vdc gate ? to ? source voltage ? continuous ? non ? repetitive (t p 10 ms) v gs v gsm 20 25 vdc vpk drain current ? continuous drain current ? continuous @ 100 c drain current ? single pulse (t p 10 s) i d i d i dm 1.7 1.4 6.0 adc apk total pd @ t a = 25 c mounted on 1 sq. drain pad on fr ? 4 bd material total pd @ t a = 25 c mounted on 0.70 sq. drain pad on fr ? 4 bd material total pd @ t a = 25 c mounted on min. drain pad on fr ? 4 bd material derate above 25 c p d 2.1 1.7 0.94 6.3 w mw/ c operating and storage temperature range t j , t stg ? 55 to 175 c single pulse drain ? to ? source avalanche energy ? starting t j = 25 c (v dd = 25 vdc, v gs = 10 vdc, peak i l = 3.4 apk, l = 10 mh, r g = 25 ) e as 58 mj thermal resistance ? junction to ambient on 1 sq. drain padon fr ? 4 bd material ? junction to ambient on 0.70 sq. drain pad on fr ? 4 bd material ? junction to ambient on min. drain pad on fr ? 4 bd material r ja r ja r ja 70 88 159 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 s t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1 ampere, 60 volts r ds(on) = 130 m d g s 1 2 3 4 n ? channel device package shipping ? ordering information mmft3055vt1 sot ? 223 1000 tape & reel to ? 261aa case 318e style 3 a = assembly location y = year w = work week = pb ? free package v3055 = device code marking diagram and pin assignment 3 source 2 drain 1 gate 4 drain MMFT3055VT1G sot ? 223 (pb ? free) 1000 tape & reel http://onsemi.com (note: microdot may be in either location) ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. ayw v3055
mmft3055v http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain ? to ? source breakdown voltage (cpk 2.0) (note 3) (v gs = 0 vdc, i d = 0.25 madc) temperature coefficient (positive) v (br)dss 60 ? ? 63 ? ? vdc mv/ c zero gate voltage drain current (v ds = 60 vdc, v gs = 0 vdc) (v ds = 60 vdc, v gs = 0 vdc, t j = 150 c) i dss ? ? ? ? 10 100 adc gate ? body leakage current (v gs = 20 vdc, v ds = 0 vdc) i gss ? ? 100 nadc on characteristics (note 1) gate threshold voltage (cpk 2.0) (note 3) (v ds = v gs , i d = 250 adc) threshold temperature coefficient (negative) v gs(th) 2.0 ? 2.8 5.6 4.0 ? vdc mv/ c static drain ? to ? source on ? resistance (cpk 2.0) (note 3) (v gs = 10 vdc, i d = 0.85 adc) r ds(on) ? 0.115 0.13 drain ? to ? source on ? voltage (v gs = 10 vdc, i d = 1.7 adc) (v gs = 10 vdc, i d = 0.85 adc, t j = 150 c) v ds(on) ? ? ? ? 0.27 0.25 vdc forward transconductance (v ds = 8.0 vdc, i d = 1.7 adc) g fs 1.0 2.7 ? mhos dynamic characteristics input capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz) c iss ? 360 500 pf output capacitance c oss ? 110 150 transfer capacitance c rss ? 25 50 switching characteristics (note 2) turn ? on delay time (v dd = 30 vdc, i d = 1.7 adc, v gs = 10 vdc, r g = 9.1 ) t d(on) ? 8.0 20 ns rise time t r ? 9.0 20 turn ? off delay time t d(off) ? 32 60 fall time t f ? 18 40 gate charge (v ds = 48 vdc, i d = 1.7 adc, v gs = 10 vdc) q t ? 13 20 nc q 1 ? 2.0 ? q 2 ? 5.0 ? q 3 ? 4.0 ? source ? drain diode characteristics forward on ? voltage (note 1) (i s = 1.7 adc, v gs = 0 vdc) (i s = 1.7 adc, v gs = 0 vdc, t j = 150 c) v sd ? ? 0.85 0.7 1.6 ? vdc reverse recovery time (i s = 1.7 adc, v gs = 0 vdc, di s /dt = 100 a/ s) t rr ? 40 ? ns t a ? 34 ? t b ? 6.0 ? reverse recovery stored charge q rr ? 0.089 ? c internal package inductance internal drain inductance (measured from the drain lead 0.25 from package to center of die) l d ? 4.5 ? nh internal source inductance (measured from the source lead 0.25 from package to source bond pad) l s ? 7.5 ? nh 1. pulse test: pulse width 300 s, duty cycle 2%. 2. switching characteristics are independent of operating junction temperature. 3. reflects typical values. c pk = max limit ? typ 3 x sigma
mmft3055v http://onsemi.com 3 typical electrical characteristics r ds(on) , drain?to?source resistance (ohms) r ds(on) , drain?to?source resistance (normalized) 01 2345 0 1.5 2.5 v ds , drain?to?source voltage (volts) figure 1. on ? region characteristics i d , drain current (amps) 234 56 0 1.5 3 4 i d , drain current (amps) v gs , gate?to?source voltage (volts) figure 2. transfer characteristics 0 0.5 1 2.5 4 0 0.05 0.1 0.15 r ds(on) , drain?to?source resistance (ohms) 0 1 3.5 4 0.050 0.065 0.140 0.170 i d , drain current (amps) figure 3. on ? resistance versus drain current and temperature i d , drain current (amps) figure 4. on ? resistance versus drain current and gate voltage ?50 0.6 0.8 1.2 1.6 020 5060 10 100 1000 t j , junction temperature ( c) figure 5. on ? resistance variation with temperature v ds , drain?to?source voltage (volts) figure 6. drain ? to ? source leakage current versus voltage i dss , leakage (na) ?25 0 25 50 75 100 125 150 t j = 25 c v ds 10 v t j = ?55 c 25 c 100 c t j = 25 c v gs = 0 v v gs = 10 v v gs = 10 v i d = 0.85 a 5 v 4 v 3.5 v 4.5 v 0.5 1 2 2.5 3.5 4.5 5.5 0.5 2 3.5 v gs = 10 v t j = 100 c 25 c ?55 c 2 3.5 0.5 2 2.5 10 30 40 0.025 0.075 0.125 0.080 0.155 0.095 1.0 1.4 t j = 125 c v gs = 10 v 15 v 175 678910 2.5 1 3 1.5 0.175 0.2 0.125 1.5 3 0.110 0.4 0.2 0 1.8 2.0 100 c 3 3.5 4 7 v 6 v 5.5 v 6.5 7 7.5 0.225 0.25 525 55 15 35 45
mmft3055v http://onsemi.com 4 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because drain ? gate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in mo st cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg ? v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turn ? on and turn ? off delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg ? v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the off ? state condition when calculating t d(on) and is read at a voltage corresponding to the on ? state when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. 10 0 10 15 25 gate?to?source or drain?to?source voltage (volts) c, capacitance (pf) figure 7. capacitance variation v gs v ds t j = 25 c v ds = 0 v v gs = 0 v 600 500 400 300 200 100 0 20 c iss c oss c rss 55 c iss c rss 800 900 700 1000 1100
mmft3055v http://onsemi.com 5 drain ? to ? source diode characteristics 0.5 0.55 0.65 0.85 v sd , source?to?drain voltage (volts) i s , source current (amps) figure 8. gate ? to ? source and drain ? to ? source voltage versus total charge r g , gate resistance (ohms) 1 10 100 t, time (ns) v dd = 30 v i d = 1.7 a v gs = 10 v t j = 25 c t f t d(off) v gs = 0 v t j = 25 c 0 1.2 1.6 2 1000 100 10 1 0.8 0.6 0.7 0.75 0.4 0.8 t d(on) t r figure 9. resistive switching time variation versus gate resistance 1 1.4 1.8 0.6 0.2 0.9 v ds , drain?to?source voltage (volts) v gs , gate?to?source voltage (volts) figure 10. diode forward voltage versus current 0 q t , total charge (nc) 2468 i d = 1.7 a t j = 25 c v gs 10 6 2 0 1 8 4 30 27 24 21 18 15 0 v ds 14 qt q1 q2 q3 10 12 7 3 9 5 12 3 6 9 safe operating area the forward biased safe operating area curves define the maximum simultaneous drain ? to ? source voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, ?transient thermal resistance ? general data and its use.? switching between the off ? state and the on ? state may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded and the transition time (t r ,t f ) do not exceed 10 s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) ? t c )/(r jc ). a power mosfet designated e ? fet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy , avalanche energy capability is not a constant. the energy rating decreases non ? linearly with an increase of peak current in avalanche and peak junction temperature. although many e ? fets can withstand the stress of drain ? to ? source avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous current (i d ), in accordance with industry custom. the energy rating must be derated for temperature as shown in the accompanying graph (figure 13). maximum energy at currents below rated continuous i d can safely be assumed to equal the values indicated.
mmft3055v http://onsemi.com 6 safe operating area t j , starting junction temperature ( c) e as , single pulse drain?to?source figure 11. maximum rated forward biased safe operating area 0.1 10 100 v ds , drain?to?source voltage (volts) figure 12. maximum avalanche energy versus starting junction temperature avalanche energy (mj) i d , drain current (amps) 25 50 75 100 125 v gs = 20 v single pulse t c = 25 c i d = 1.7 a 1.0 150 figure 13. thermal response figure 14. diode reverse recovery waveform di/dt t rr t a t p i s 0.25 i s time i s t b 0.1 10 0.01 0 30 10 1 r ds(on) limit thermal limit package limit 20 175 40 50 60 dc 100 ms 500 ms 1 s 10 ms t, time (s) rthja(t), effective transient thermal resistance 0.1 0.01 0.001 d = 0.5 single pulse 1.0e?05 1.0e?04 1.0e?03 1.0e?02 1.0e?01 1.0e+00 1.0e+01 0.2 0.1 0.05 0.02 0.01 1.0e+02 1.0e+03 0.0001 1
mmft3055v http://onsemi.com 7 package dimensions sot ? 223 (to ? 261) case 318e ? 04 issue l a1 b1 d e b e e1 4 123 0.08 (0003) a l1 c notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 1.5 0.059 mm inches scale 6:1 3.8 0.15 2.0 0.079 6.3 0.248 2.3 0.091 2.3 0.091 2.0 0.079 soldering footprint* h e dim a min nom max min millimeters 1.50 1.63 1.75 0.060 inches a1 0.02 0.06 0.10 0.001 b 0.60 0.75 0.89 0.024 b1 2.90 3.06 3.20 0.115 c 0.24 0.29 0.35 0.009 d 6.30 6.50 6.70 0.249 e 3.30 3.50 3.70 0.130 e 2.20 2.30 2.40 0.087 0.85 0.94 1.05 0.033 0.064 0.068 0.002 0.004 0.030 0.035 0.121 0.126 0.012 0.014 0.256 0.263 0.138 0.145 0.091 0.094 0.037 0.041 nom max l1 1.50 1.75 2.00 0.060 6.70 7.00 7.30 0.264 0.069 0.078 0.276 0.287 h e ? ? e1 0 1 0 0 1 0 style 3: pin 1. gate 2. drain 3. source 4. drain *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 mmft3055v/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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